There is increasing interest in graphics systems that utilize a partitioned graphics memory. Background information on partitioned graphics memories is described in U.S. Pat. No. 6,853,382 by Van Dyke et al., the contents of which are hereby incorporated by reference. A partitioned graphics memory has a number of partitions that are each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to a naïve memory client of a unitary memory system.
A partitioned graphics memory provides several advantages. One advantage is that since conventional dynamic random access memories (DRAMs) come in a limited number of standard sizes, a partitioned graphics memory allows an increase in the effective memory size, which improves performance.
As one example of a partitioned graphics memory, FIG. 1 illustrates a memory system 100 similar to that described in U.S. patent Ser. No. 10/740,229 by Van Dyke et al., the contents of which are hereby incorporated by reference. A memory system 100 for a partitioned memory system 100 includes two or more memory partitions, with the total number of partitions being equal to a power of two, such as four partitions. Each partition P0 115, P1 120, P2 125, and P3 130 is coupled to a memory controller 105 by its own respective data bus 135. Each data bus 135 has a memory byte width, Wp, with an associated packet width for addressing locations within the partition. In accord with a common usage in the graphics industry a packet is a unit of data transfer.
In turn, each partition may have sub-partitions, such as two sub-partitions SP0 140A and SP1 140B. Each sub-partition 140A and 140B has its own respective sub-bus 148 with a corresponding byte width for sub-packets. Wsp, addressed to a memory location in the sub-partition. Thus, in a single memory access to a partition, Pi, a single memory access may be made to each of its sub-partitions SPi. The sub-partitions are thus the minimum addressable unit of the graphics system. Each sub-partition may, for example, be a double data rate (DDR) dynamic random access memory (DRAM). As an illustrative example, each partition may have 64 data pins whereas each sub-partition 140A or 140B has 32 data pins. This permits, for example, a 64 bit partition to be implemented as two conventional 32 bit memory chips.
The memory controller 105 routes addresses of requests from individual clients of a graphics system to specific partition/sub-partition memory locations. The individual clients may be any component within a graphics processing system that requires access to a graphics memory to read, write, clear, or compress tile data. An arbitration module 150 selects a client 155 or 160.
A partition address routing module 190 maps an address associated with a client (e.g., a read or write request) to a memory location in a partition and its associated sub-partitions. A compression/decompression module 165 is included to compress and decompress tile data to reduce memory bandwidth requirements. A tag module 170 may be included to identify, by a tag (e.g., one or more bits) attributes of the tiles, such as whether a tile holds data in a compressed format. A packing/unpacking state machine 180 and format conversion module 195 are provided to reorganize tile data.
As previously described, partitioning permits the total effective number of DRAM data pins to be increased compared to an individual DRAM. The total effective number of data pins for the partitioned graphics memory is the number of data pins per partition multiplied by the number of partitions. As graphics systems have evolved, the equivalent DRAM memory size of partitioned graphics memories have increased from 128 pins (27) to 256 pins (28) in current generation products. For example, a total DRAM address space corresponding to 256 pins (which is a power of two, i.e., 256=28) may be implemented with four partitions each having 64 DRAM pins.
Conventionally, the number of DRAMs in a partitioned graphics memory is a power of two. As is well known, binary address spaces naturally scale as a power of two. Additionally, many other attributes of a computer system also typically scale as a power of two. As a consequence, conventional partitioned graphics memories utilize a power of two number of partitions (e.g., four) and have a power of two number of DRAMs (e.g., eight DRAMs in a partitioned graphics memory having four partitions and two DRAMs per partition).
However, doubling the number of DRAMs in successive product generations increases costs and also tends to reduce yield due to the larger chip area that is required. Consequently, it would be desirable to support an arbitrary number of partitions.
In light of the above-described problems the apparatus, system and method of the present invention was developed.